A configuration as shown in FIG. 1, for example, is known as a duty correction circuit used in a delay lock loop (Delay Lock Loop) or the like. FIG. 1 is based on FIG. 2 in Patent Document 1. In FIG. 1, circuit blocks, names of signals, reference numerals are different from those in FIG. 2 in Patent Document 1 (In FIG. 1, an rst signal and a reset terminal of FIG. 2 in Patent Document 1 are omitted).
Referring to FIG. 1, the duty correction circuit includes a duty control buffer 10 that differentially receives complementary input signals IN1 and INB1 and a duty control voltage generator 20 that receives signals OUT1 and OUTB1 output differentially from the duty control buffer 10, detects a duty error between the signals OUT1 and OUTB1, and differentially outputs a first duty control voltage signal VCNT1 and a second duty control voltage signal VCNTB1 corresponding to the duty error. In the duty control voltage generator 20, respective potentials of the signals OUT1 and OUTB1 are integrated. Then, an amount of duty deterioration (time difference between a High level period and a Low level period) is converted to a potential difference between the first duty control voltage signal VCNT1 and the second duty control voltage signal VCNTB. In the duty control buffer 10, the potential difference between the first duty control voltage signal VCNT1 and the second duty control voltage signal VCNTB1 is converted to a difference voltage between respective center voltages (offsets) of the signals OUT1 and OUTB to perform duty correction.
[Patent Document 1] JP Patent Kokai Publication No. JP-P-2005-136949A